diff -urN gcc-4.5.2-orig/gcc/config/sparc/leon3.md gcc-4.5.2/gcc/config/sparc/leon3.md
--- gcc-4.5.2-orig/gcc/config/sparc/leon3.md	1970-01-01 01:00:00.000000000 +0100
+++ gcc-4.5.2/gcc/config/sparc/leon3.md	2011-01-29 17:13:24.000000000 +0100
@@ -0,0 +1,97 @@
+;; Scheduling description for LEON3.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;;
+;; The LEON3 is a single-issue processor.
+;; Most instructions execute in one cycle. Some instructions require one or
+;; two extra cycle in case of a data dependency.
+;;
+;; Cycle timing of the LEON3 is somewhat dependent on synthesis options.
+;; This file is aimed at a common configuration: 5-cycle hardware multiplier,
+;; 1 cycle load delay, no branch prediction, fast TLB.
+;;
+
+(define_automaton "leon3_0")
+
+(define_cpu_unit "leon3_pipe, leon3_fpu" "leon3_0")
+
+(define_insn_reservation "leon3_ialu" 1
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "ialu,ialuX,shift"))
+  "leon3_pipe")
+
+(define_insn_reservation "leon3_compare" 1
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "compare"))
+  "leon3_pipe")
+
+(define_insn_reservation "leon3_load" 2
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "load,sload,fpload"))
+  "leon3_pipe, nothing")
+
+(define_insn_reservation "leon3_store" 2
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "store,fpstore"))
+  "leon3_pipe*2")
+
+(define_insn_reservation "leon3_mul" 6
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "imul"))
+  "leon3_pipe*5, nothing")
+
+(define_insn_reservation "leon3_div" 35
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "idiv"))
+  "leon3_pipe*35")
+
+(define_insn_reservation "leon3_branch" 1
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "branch"))
+  "leon3_pipe")
+
+(define_insn_reservation "leon3_fp" 4
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "fp,fpmove,fpcmp,fpmul"))
+  "leon3_pipe, nothing*3")
+
+(define_insn_reservation "leon3_fpdiv" 16
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "fpdivs,fpdivd"))
+  "leon3_pipe, leon3_fpu*14, nothing")
+
+(define_insn_reservation "leon3_fpsqrt" 24
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "fpsqrts,fpsqrtd"))
+  "leon3_pipe, leon3_fpu*22, nothing")
+
+; Catch-all reservation for all other instruction types.
+; Without this reservation, the scheduler will think it can issue these
+; instructions at zero cost in parallel with a store or mul.
+(define_insn_reservation "leon3_misc" 1
+  (and (eq_attr "cpu" "leon3")
+    (eq_attr "type" "uncond_branch,call,sibcall,call_no_delay_slot,return,multi,savew"))
+  "leon3_pipe")
+
+(define_bypass 3 "leon3_compare" "leon3_branch")
+
+(define_bypass 1 "leon3_load" "leon3_store"
+  "store_data_bypass_p")
+
+(define_bypass 5 "leon3_mul" "leon3_store"
+  "store_data_bypass_p")
diff -urN gcc-4.5.2-orig/gcc/config/sparc/sparc.c gcc-4.5.2/gcc/config/sparc/sparc.c
--- gcc-4.5.2-orig/gcc/config/sparc/sparc.c	2010-08-07 01:23:12.000000000 +0200
+++ gcc-4.5.2/gcc/config/sparc/sparc.c	2011-01-31 20:51:19.000000000 +0100
@@ -152,6 +152,32 @@
 };
 
 static const
+struct processor_costs leon3_costs = {
+  COSTS_N_INSNS (2), /* int load */
+  COSTS_N_INSNS (2), /* int signed load */
+  COSTS_N_INSNS (2), /* int zeroed load */
+  COSTS_N_INSNS (2), /* float load */
+  COSTS_N_INSNS (4), /* fmov, fneg, fabs */
+  COSTS_N_INSNS (4), /* fadd, fsub */
+  COSTS_N_INSNS (4), /* fcmp */
+  COSTS_N_INSNS (4), /* fmov, fmovr */
+  COSTS_N_INSNS (4), /* fmul */
+  COSTS_N_INSNS (15), /* fdivs */
+  COSTS_N_INSNS (15), /* fdivd */
+  COSTS_N_INSNS (23), /* fsqrts */
+  COSTS_N_INSNS (23), /* fsqrtd */
+  COSTS_N_INSNS (5), /* imul */
+  COSTS_N_INSNS (5), /* imulX */
+  0, /* imul bit factor */
+  COSTS_N_INSNS (35), /* idiv */
+  COSTS_N_INSNS (35), /* idivX */
+  COSTS_N_INSNS (1), /* movcc/movr */
+  1, /* shift penalty */
+/* Note: There is no penalty for 32-bit shift on LEON3. But shift_penalty
+   helps to avoid expensive 64-bit shift if an alternative is available. */
+};
+
+static const
 struct processor_costs ultrasparc_costs = {
   COSTS_N_INSNS (2), /* int load */
   COSTS_N_INSNS (3), /* int signed load */
@@ -687,6 +713,7 @@
     { "sparclite86x",  PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
       MASK_SPARCLITE },
     { "sparclet",   PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
+    { "leon3",      PROCESSOR_LEON3, MASK_ISA, MASK_V8 },
     /* TEMIC sparclet */
     { "tsc701",     PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
     { "v9",         PROCESSOR_V9, MASK_ISA, MASK_V9 },
@@ -854,6 +881,9 @@
     case PROCESSOR_TSC701:
       sparc_costs = &sparclet_costs;
       break;
+    case PROCESSOR_LEON3:
+      sparc_costs = &leon3_costs;
+      break;
     case PROCESSOR_V9:
     case PROCESSOR_ULTRASPARC:
       sparc_costs = &ultrasparc_costs;
diff -urN gcc-4.5.2-orig/gcc/config/sparc/sparc.h gcc-4.5.2/gcc/config/sparc/sparc.h
--- gcc-4.5.2-orig/gcc/config/sparc/sparc.h	2010-11-20 23:05:08.000000000 +0100
+++ gcc-4.5.2/gcc/config/sparc/sparc.h	2011-01-24 22:18:35.000000000 +0100
@@ -541,6 +541,7 @@
   PROCESSOR_SPARCLITE86X,
   PROCESSOR_SPARCLET,
   PROCESSOR_TSC701,
+  PROCESSOR_LEON3,
   PROCESSOR_V9,
   PROCESSOR_ULTRASPARC,
   PROCESSOR_ULTRASPARC3,
diff -urN gcc-4.5.2-orig/gcc/config/sparc/sparc.md gcc-4.5.2/gcc/config/sparc/sparc.md
--- gcc-4.5.2-orig/gcc/config/sparc/sparc.md	2010-04-02 21:54:46.000000000 +0200
+++ gcc-4.5.2/gcc/config/sparc/sparc.md	2011-01-24 22:19:01.000000000 +0100
@@ -106,6 +106,7 @@
    sparclite,f930,f934,
    hypersparc,sparclite86x,
    sparclet,tsc701,
+   leon3,
    v9,
    ultrasparc,
    ultrasparc3,
@@ -339,6 +340,7 @@
 (include "supersparc.md")
 (include "hypersparc.md")
 (include "sparclet.md")
+(include "leon3.md")
 (include "ultra1_2.md")
 (include "ultra3.md")
 (include "niagara.md")
